The present invention relates to improvement of a semiconductor storage device such as a cache memory.
A recent microprocessor is generally provided with a high-speed cache memory disposed between a CPU and a low-speed main mass storage device in order to improve the entire performance.
A cache memory is described in detail in, for example, "Computer Architecture: A Quantitative Approach" written by John L. Hennessy and David A. Patterson, published by Morgan Knafmann Publishers, Inc. (1990).
A control system for a cache memory is basically classified into the following two systems respectively adopting different write methods: a write through (store in) system and a write back system. In the write through system, both the cache memory and the main storage device are written. In contrast, in the write back system, merely the cache memory is written, and when a block in the cache memory where data has been changed is to be rewritten, the data is written in the main storage device.
FIG. 8 illustrates such a conventional cache memory, and is a block diagram for showing an exemplified configuration of the cache memory and peripheral related equipment.
In FIG. 8, a reference numeral 1 denotes a microprocessor, whose composing elements relating to the invention alone are shown in FIG. 8. A reference numeral 3 denotes a CPU, a reference numeral 4 denotes an external main storage device, a reference numeral 5 denotes a bus controller, a reference numeral 6 denotes an address bus, a reference numeral 7 denotes a data bus, a reference numeral 8 denotes a cache memory and a reference numeral 9 denotes a write back buffer.
In the cache memory having the aforementioned configuration, a write operation in the cache memory 8 by the write back system will now be described.
The address bus 6 transfers an address signal supplied by the CPU 3 to the cache memory 8 and also to the main storage device 4 through the bus controller 5. The data bus 7 transfers data between the cache memory 8 or the main storage device 4 and the CPU 3. The bus controller 5 controls the address bus 6 and the data bus 7 between the bus controller 5 and the main storage device 4. Also, a minimum unit of data transferred between the cache memory 8 and the main storage device 4 is designated as a block or a line, and the size of a block is generally larger than, for example, an integral number of times as large as a data width (bit number) of data transferred between the cache memory 8 and the data bus 7 in a batch.
When an arbitrary address in the cache memory 8 is to be written, when data of a block (or a line; hereinafter represented by the "block") including the address to be written is not changed (rewritten) while the data is being held in the cache memory 8, the same data remains in the main storage device 4, and hence, there is no need to write back the data in the main storage device 4. On the other hand, when the data of the block including the address to be written is changed while the data is being held in the cache memory 8, the data in the block is different from data in the main storage device 4, and hence, it is necessary to write back the data of the block in the main storage device 4 before writing new data in the cache memory 8.
While the data is being written back in the main storage device 4, a data write operation in the cache memory 8 is necessary to be waited. Since a data write operation in the main storage device 4 is conducted at a very low speed, the write back buffer 9 is used for temporarily holding the data to be written back in the main storage device 4 so that waiting time can be shortened.
In other words, when data of a block including an address to be written in a write operation in the cache memory 8 is necessary to be written back in the main storage device 4, the data of the block is first read from the cache memory 8 and is saved in the write back buffer 9 through the data bus 7. Then, the write operation in the cache memory 8 is conducted, and the data saved in the write back buffer 9 is written back in the low-speed main storage device 4 by utilizing spare time.
In the conventional configuration, however, the write back buffer 9 is provided as an external circuit of the cache memory 8, and hence, the write (save) operation in the write back buffer 9 should be conducted through the data bus 7. Data to be saved in the write back buffer 9 corresponds to all data of a minimum unit transferred between the cache memory 8 and the main storage device 4, namely, all data of the block including the address to be written, and the block size is several times as large as the data width of data transferred between the cache memory 8 and the data bus 7 in a batch. Therefore, in order to save the data of one block in the write back buffer 9, it is necessary to make several accesses to the cache memory 8 to read the data. For example, in the case where the data width of data transferred between the cache memory 8 and the data bus 7 in a batch is 32 bits and the block size is 128 bits (16 bytes), at least four accesses should be made to the cache memory 8 in order to save the data of one block in the write back buffer 9. Accordingly, the throughput of the entire system using the microprocessor 1 can be disadvantageously degraded.
Furthermore, since the number of accesses made to the cache memory 8 is increased, the power consumed by the microprocessor 1 can be disadvantageously increased.
In addition, the write back buffer 9 is required to hold data of a block with a large size. Therefore, even when the write back buffer 9 is constructed by using, for example, a generally used flip-flop and the like, the write back buffer 9 occupies a large area, resulting in increasing the chip area.